This application claims priority to Korean Patent Application No. 2005-61863, filed on Jul. 8, 2005 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to error correction in data converters such as analog-to-digital converters, and more particularly, to correcting for bubble errors in an analog-to-digital converter having interpolation.
2. Description of the Related Art
An analog-to-digital converter (ADC) that converts an analog signal into a digital code is widely used in various electronic devices such as display devices, computers, home appliances, and communication systems. The ADC is becoming more important for image signal processing applications as multimedia services become popular.
The ADC is typically included in a system as a subordinate block that intermediates between an analog block and a digital block for signal transfer, thereby directly affecting the performance of the system. Thus, various types of ADCs have been developed for enhancing the performance of the system.
A flash ADC is most frequently used for fast performance, and a pipelined ADC having small size is used for slow performance. An interpolating flash ADC is used for improving input signal resolution, and a folding-interpolating ADC uses interpolation and folding techniques to preprocess an input signal.
FIG. 1 shows a circuit diagram of a conventional flash ADC, and FIG. 2 is a table listing examples of bubble errors within the ADC of FIG. 1. Referring to FIG. 1, a flash ADC 5 includes a reference voltage generator 1 for generating a plurality of reference voltages having different voltage levels. The flash ADC 5 also includes a plurality of comparators 2 for comparing an input signal Vin and the reference voltages to generate decision codes. An encoder 3 of the flash ADC 5 encodes the decision codes into a digital code representing the input signal Vin. A plurality of preamplifiers (not shown) may be disposed before the comparators.
The decision codes from the comparators 2 are referred to as thermometer codes that ideally have a distinctive boundary between sequential ‘1’s and ‘0’s. The encoder 3 detects such a boundary to generate the corresponding digital code for representing the input signal Vin.
The boundary between the sequential ‘1’s and ‘0’s in the thermometer codes conveys important information. Thus, the thermometer codes should ideally have only one clear boundary like EXAMPLE 5 in FIG. 2. Unfortunately, the thermometer codes more typically have an irregular distribution of ‘1’s and ‘0’s near such a desired boundary as illustrated by EXAMPLEs 1, 2, 3, and 4 in FIG. 2.
The irregular distribution of ‘1’s and ‘0’s is referred to as bubble errors because the irregular distribution seems like bubbles at the top level of a liquid in a thermometer. Such bubble errors are caused by many factors, such as the meta-stability of the comparator 2 operating in synchronization with a high-speed clock during a transition of the decision codes, a kickback noise from a clock signal, by a large signal component, or a bandwidth limitation.
The dotted line in FIG. 2 represents an estimated boundary (referred to as a ‘Best Guess’) between ‘1’s and ‘0’s with the bubble errors. The estimated boundary is desired to be the ideal boundary of EXAMPLE 5. The comparators 2 may include a bubble error rejecter for removing the bubble errors when generating the thermometer codes.
FIG. 3 shows a conventional flash ADC with a bubble error rejecter 20 for correcting thermometer codes generated by a plurality of sequential comparators 11, 12, 13, 14, and 15. Each of a plurality of voters 21, 22, 23, 24, and 25 within the bubble error rejecter 20 is coupled to a respective one of the comparators 11, 12, 13, 14, and 15 for correcting a respective one of the thermal codes C1, C2, C3, C4, and C5.
Each voter 21, 22, 23, 24, or 25 receives the respective one of the thermal codes C1, C2, C3, C4, or C5 and two adjacent thermal codes from two adjacent comparators (as illustrated in FIG. 3). FIG. 4 shows a circuit diagram of an example voter 22 in FIG. 3 receiving the three thermal codes C1, C2, and C3. The example voter 22 includes NAND gates 41, 42, and 43 with inverters 51, 52, and 53, and an OR gate 60, configured as illustrated in FIG. 4.
With such a configuration of FIG. 4, the example voter 22 outputs a majority bit value among the bit values of the three thermometer codes C1, C2 and C3, to generate a correction code C2′ (i.e., T2 in FIG. 3). For example, when the bit values for the three thermometer codes C1, C2 and C3 are respectively ‘1’, ‘0’ and ‘1’, the second voter 22 outputs the majority bit value ‘1’. Alternatively, when the bit values of the three thermometer codes C1, C2 and C3 are respectively ‘0’, ‘0’ and ‘1’, the second voter 22 outputs the majority bit value ‘0’. Each of the other voters 21, 23, 24, and 25 in FIG. 3 operates similarly to generate the correction codes T1, T3, T4, and T5, respectively.
FIG. 5 shows a state diagram illustrating a process of removing the bubble errors by the bubble error rejecter 20 in FIG. 3. Referring to FIGS. 3, 4 and 5, a bubble error occurs when the second comparator 12 outputs ‘0’ and the third comparator 13 outputs ‘1’. In this example, the second voter 22 receives thermometer codes ‘1’, ‘0’ and ‘1’ and generates the majority bit value ‘1’. The third voter 23 receives thermometer codes ‘0’, ‘1’ and ‘0’ and generates the majority bit value ‘0’. In this manner, the bubble errors are corrected by the second and third voters 22 and 23.
However, because the conventional bubble error rejecter determines the majority bit value from three sequential thermometer codes, bubble errors spanning two or more bits may not be properly corrected. Particularly, in an interpolating flash ADC or a folding-interpolating ADC, bubble errors spanning many bits occur frequently. In that case, the conventional bubble error rejecter may not completely remove the bubble errors.